1. Field of Invention
The present invention generally relates to buffers, and more particularly to input buffers and input-output buffers, which are in full compliance with IDDQ testability.
2. Description of Related Art
Integrated circuits (IC) are now used everywhere in the world. There is no exaggeration to say that ICs are indispensable to the day-to-day life of human being. However, fabrication processes of ICs are very complicated. There are hundreds of steps involved, and a time frame of one or two months is required to make an IC. Basically, the IC industry includes four branches, namely, IC design, wafer fabrication, testing, and packaging, which are combined together to build this high-technology industry. It is therefore not only an industry of advanced technology, but also an industry of high risk, which requires tremendous capital to support its continuous development.
In order to distinguish good semiconductor components, for example, ICs, from bad ones, various tests are required after all the fabrication processes are completed. Quiescent-current testing, or IDDQ for abbreviation, is one of the tests, which is widely used to determine if there exist any short or bridge errors in semiconductor components. If the errors are found in a component under an IDDQ testing, appropriate measurements need to be taken, such as selling it in lower prices, or even discarding it totally.
When ICs are tested and packaged, they can then be applied to practical circuits. Conventionally, external resistors are added to input-output (I/O) pins in many applied circuits, so as to provide a stable certain default input-output state and reduce interference from noises. The external resistors, however, take extra space and increase production cost, which is not economical.
To solve the space-taking problem, resistors are accordingly constructed within the integrated circuits to avoid the cost problem. It is worth noting that the resistors chosen have a significant impact on the biased current of the IC. For example, assume a resistor connected to an input-output line, which has a resistance value ranged between 10K.OMEGA. to 50K.OMEGA.. If a 50-K.OMEGA. resistor is used, the biased current is about 5V/50K.OMEGA.=0.1 mA when the voltage across the resistor is 5V. However, resistance variation for a resistor in the fabrication process is about .+-.60%. If there are ten input-output lines, the variation range of the produced biased current is about 1 mA.+-.60%=600 .mu.A.
In another aspect, the fault conducting current obtained due to a short or bridge circuit in an IC under testing is ranged between 10 .mu.A to 100 .mu.A. That is, when a current measured in an IDDQ testing is larger than 10.mu.A, errors have occurred in the IC under testing.
Therefore, the biased current with a variation range of 600 .mu.A will result in a failure to distinguish whether the problem is resulted from the short or bridge circuit of an IC or from the variation range of the 600 .mu.A biased current during an IDDQ testing. It is impossible to have accurate testing results under this circumstance. To solve this problem, the resistor needs to be replaced by a high-impedance one. For example, the 50-K.OMEGA. resistor is replaced by a 5-M.OMEGA. resistor. Another problem arises, however, since the high-impedance resistors used within ICs are susceptible to interference during operations, causing instability problem or even failure. Furthermore, the operating speed is also reduced because of the high-impedance resistors.
Conventionally, pullup or pulldown resistors in an input buffer need to be smaller than 100K.OMEGA. so as to meet the speed requirements. It is then impossible to perform the IDDQ testing because the variation of the biased current due to the resistor is far larger than that of the fault conducting current. Therefore, it is necessary to use a high-state input voltage for the input buffer if a pullup resistor coupled to a voltage source is used, and a low-state input voltage for the input buffer if a pulldown resistor coupled to a ground is used, so that the IDDQ testing can be performed because there is no voltage drop across the resistor to produce the undesired biased current. Unfortunately, these conditions are too strict to generally apply to all applications, resulting in failure in performing the IDDQ testing for some applications.